17–22
Chapter 17: Gate & Control Library
Figure 17–14 shows an example with the Multiplexer block.
Figure 17–14. Multiplexer Block Example
Pattern
The Pattern block generates a repeating periodic bit sequence in time. You can enter
the required pattern as a binary sequence.
For example, the pattern 01100 outputs the repeating pattern:
0110001100011000110001100011000110001100
You can change the output data rate for a registered block by feeding the clock enable
input with the output of the Pattern block.
1
With a sequence of length 1, the Pattern block acts as a constant, holding its output to
the specified value at all times. There is no artificial limit to the pattern length.
Table 17–37 shows the Pattern block inputs and outputs.
Table 17–37. Pattern Block Inputs and Outputs
Signal
ena
sclr
<unnamed>
Direction
Input
Input
Output
Description
Optional clock enable port.
Optional synchronous clear port.
Output data port.
Table 17–38 shows the Pattern block parameters.
Table 17–38. Pattern Block Parameters
Name
Binary Sequence
Specify Clock
DSP Builder Handbook
Value
User Defined
On or Off
Description
Specify the sequence that you want to use.
Turn on to explicitly specify the clock name.
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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